1. Field of the Invention
This invention relates to a lead-bond type chip package, and more specifically to a multilayer substrate for use in forming the lead-bond type chip package. This invention also pertains to a method for making the multilayer substrate.
2. Description of the Related Art
FIG. 1 depicts a conventional lead-bond type chip package 100 comprising a semiconductor chip 130 disposed on a substrate 120 through an elastomer pad 110. The semiconductor chip 130 has a plurality of bonding pads 132 disposed thereon. The substrate 120 includes a plurality of solder pads 122 and leads 124 provided on the upper surface thereof. The solder pads 122 are electrically connected to corresponding leads 124 through conductive traces on the substrate 120. The substrate 120 has a plurality of through-holes corresponding to the solder pads 122 such that each of the solder pads 122 has at least a portion exposed from its corresponding through-hole for mounting a solder ball 126. The leads 124 are bonded to corresponding bonding pads 132 thereby electrically connecting the semiconductor chip 130 to the substrate 120. A package body 140 is formed around the semiconductor chip 130 and filled the slot 120a of the substrate 120. The package body 140 is formed from insulating material such as epoxy resin.
The substrate 120 is typically made from flexible polyimide film; hence, it is prone to be deformed by external forces (e.g. stress due to CTE (coefficient of thermal expansion) mismatch) thereby resulting in problems of die cracking or delamination. Further, since the substrate 120 only has a layer of conductor circuit (i.e. the solder pads 122, the leads 124, and the conductive traces), it is difficult to provide enough power and ground planes. Therefore, the conventional lead-bond type chip package 100 does not provide a good signal plane for current surges into or out of the semiconductor chip 130. The relatively poor electrical performance associated with the package 100 is especially apparent when the semiconductor chip 130 includes high density, high frequency digital circuitry.
The structures utilized to provide the first level connection between the chip and the substrate must accommodate all of the required electrical interconnections to the chip. The number of connections to external circuit elements, commonly referred to as “input-output” or “I/O” connections, is determined by the structure and function of the chip. Advanced chips capable of performing numerous functions may require substantial number of I/O connections. Therefore, it will possibly happen that some of the I/O connections of a chip can not be lead-bonded for electrical connection due to the insufficiency of wiring density in the substrate with a single layer of conductor circuit. If this were the case, multiple layer structure will be required for the chip with high I/O connections.
The present invention therefore seeks to provide a lead-bond type chip package which overcomes, or at least reduces the above-mentioned problems of the prior art.